The speeds of metal-oxide-semiconductor (MOS) transistors are closely related to the drive currents of the MOS transistors, which drive currents are further closely related to the mobility of charges. For example, NMOS transistors have high drive currents when the electron mobility in their channel regions is high, while PMOS transistors have high drive currents when the hole mobility in their channel regions is high.
Compound semiconductor materials of group III and group V elements (commonly known as III-V compound semiconductors) are good candidates for forming NMOS transistors due to their high electron mobility. Therefore, III-V compound semiconductors have been commonly used to form NMOS transistors. To reduce the manufacturing cost, methods for forming PMOS transistors using III-V compound semiconductors have also been explored. FIG. 1 illustrates a conventional transistor incorporating III-V compound semiconductors. In the formation process, a plurality of layers is blanket formed on a silicon substrate, wherein the plurality of layers includes a buffer layer formed of GaAs, a graded buffer layer formed of InxAl1-xAs (with x between, but not equal to, 0 and 1), a bottom barrier layer formed of In0.52Al0.48As, a channel layer formed of In0.7Ga0.3As, a top barrier layer formed of In0.52Al0.48As, an etch stop layer formed of InP, and a contact layer formed of In0.53Ga0.47As. A first etch is performed to etch through the contact layer (In0.53Ga0.47As) and stop at the etch stop layer (InP) to form a first recess. A second etch is then performed to etch through the etch stop layer (InP) and into a portion of the top barrier layer (In0.52Al0.48As) to form a second recess. A gate, which is formed of metal, is then formed in the second recess. The resulting transistor has the advantageous feature of a quantum well formed of the bottom barrier layer, the channel layer, and the top barrier layer.
The above-described structure and process steps, however, suffer from drawbacks. The contact layers (In0.53Ga0.47As) are horizontally spaced apart from the gate by distance S. Further, the etch stop layer (InP) has a relatively wide bandgap and has a high resistivity. Therefore, there exists a high resistance path between the metal source/drain and the channel layer. Therefore, the external resistance of the source and drain regions is high, which adversely affects the drive current of the transistor. A method and a structure for overcoming the above-described shortcomings in the prior art are thus needed.